XC2S100-5PQG208C

Spartan-II Field-Programmable Gate Array, –0.5 to 3.0 V, QFP, four DLLs, SelectRAM hierarchical memory

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Price:: US $1.00~10.00 / piece [Get Latest Price]

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PartNumber:: XC2S100-5PQG208C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-08-11

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Part Number:XC2S100-5PQG208C
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Product Summary

The XC2S100-5PQG208C Spartan-II Field-Programmable Gate Array gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S100-5PQG208C offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

Parametrics

XC2S100-5PQG208C absolute maximum ratings: (1)Supply voltage relative to GND: –0.5 to 3.0 V; (2)Supply voltage relative to GND: –0.5 to 4.0 V; (3)Input reference voltage: –0.5 to 3.6 V; (4)Input voltage relative to GND: 5V tolerant I/O: –0.5 to 5.5 V, No 5V tolerance: –0.5 to VCCO+0.5 V; (5)Voltage applied to 3-state output: 5V tolerant I/O: –0.5 to 5.5 V, No 5V tolerance: –0.5 to VCCO+0.5 V; (6)Storage temperature (ambient): –65 to +150 ℃; (7)Junction temperature: +125 ℃.

Features

XC2S100-5PQG208C features: (1)Second generation ASIC replacement technology: Densities as high as 5,292 logic cells with up to 200,000 system gates, Streamlined features based on Virtex FPGA architecture; (2)System level features: SelectRAM hierarchical memory: 16 bits/LUT distributed RAM, Configurable 4K bit block RAM, Fast interfaces to external RAM, Fully PCI compliant, Low-power segmented routing architecture, Full readback ability for verification/observability.