SAA7111AH

Product Summary

The SAA7111AH is an Enhanced Video Input Processor (EVIP) which is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/ contrast/ saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass. The pure 3.3 V CMOS circuit SAA7111A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111AH accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. The SAA7111AH then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

Parametrics

Absolute maximum ratings:(1)digital supply voltage, VDDD: -0.5 to +4.6V; (2)analog supply voltage, VDDA: -0.5 +4.6V; (3)input voltage at analog inputs, Vi(A): -0.5 VDDA + 0.5(4.6 max.) V; (4)output voltage at analog output, Vo(A): -0.5 to VDDA+0.5V; (5)input voltage at digital inputs and outputs outputs in 3-state, Vi(D): -0.5 to +5.5V; (6)output voltage at digital outputs outputs active, Vo(D): -0.5 to VDDD+0.5V; (7)voltage difference between VSSAall and VSSall, △VSS: - 100 mV; (8)storage temperature, Tstg: -65 to +150°C; (9)operating ambient temperature, Tamb: 0 to 70°C; (10)operating ambient temperature under bias, Tamb(bias): -10 to +80°C; (11)electrostatic discharge all pins note 1, Vesd: -2000 to +2000V.

Features

Features: (1)Four analog inputs, internal analog source selectors; (2)Two analog preprocessing channels; (3)Switchable white peak control; (4)Two built-in analog anti-aliasing filters; (5)Two 8-bit video CMOS analog-to-digital converters; (6)On-chip clock generator; (7)Line-locked system clock frequencies; (8)Digital PLL for horizontal-sync processing and clock generation; (9)Requires only one crystal (24.576 MHz) for all standards; (10)Horizontal and vertical sync detection; (11)User programmable luminance peaking or aperture correction; (12)Cross-colour reduction for NTSC by chrominance comb filtering; (13)PAL delay line for correcting PAL phase errors; (14)Real time status information output (RTCO); (15)Brightness Contrast Saturation (BCS) control on-chip; (16)Odd/even field identification by a non interlace CVBS input signal; (17)Fix level for RGB output format during horizontal blanking; (18)720 active samples per line on the YUV bus; (19)One user programmable general purpose switch on an output pin; (20)Built-in line-21 text slicer; (21)Power-on control; (22)Compatible with memory-based features (line-locked clock); (23)I2C-bus controlled (full read-back ability by an external controller); (24)Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64); (25)5 V tolerant digital I/O ports.

Diagrams