(China (Mainland))
Product Summary
The EP1C6Q240C8N Cyclone FPGA is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR)interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, it is a cost-effective solution for data-path applications. The EP1C6Q240C8N supports various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure EP1C6Q240C8N.
Parametrics
EP1C6Q240C8N absolute maxing ratings: (1)VCCINT Supply voltage With respect to ground: min=-0.5V, max=2.4V; VCCIO: min=-0.5V, max=4.6V; (2)VI DC input voltage: min=-0.5V, max=4.6V; (3)IOUT DC output current, per pin: min=-25mA, max=25mA; (4)TSTG Storage temperature No bias: min=65℃, max=150℃; (5)TAMB Ambient temperature Under bias: min=-65℃, max=135℃; (6)TJ Junction temperature BGA packages under bias: max=135℃.
Features
EP1C6Q240C8N features: (1)2,910 to 20,060 LEs; (2)Up to 294,912 RAM bits (36,864 bytes); (3)Supports configuration through low-cost serial configuration device; (4)Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; (5)Support for 66-MHz, 32-bit PCI standard; (6)Low speed (311 Mbps) LVDS I/O support; (7)Up to two PLLs per device provide clock multiplication and phase shifting; (8)Up to eight global clock lines with six clock resources available per logic array block (LAB) row; (9)Support for external memory, including DDR SDRAM(133 MHz), FCRAM, and single data rate (SDR) SDRAM; (10)Support for multiple intellectual property (IP) cores, including Altera. MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.
Diagrams
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 EP1C6Q240C8N |
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IC CYCLONE FPGA 5980 LE 240-PQFP |
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